1. Field of the Invention
The present invention relates to a data reading circuit of a magnetic memory, and more particularly to a data reading circuit capable of reading data of a toggle magnetic memory through a reading mode of combining a reading mode of self reference and middle-current reference bit.
2. Related Art
Magnetic random access memory (MRAM) belongs to a non-volatile memory that stores and records information according to resistance characteristics. The MRAM has the advantages of non-volatility, high density, high read/write speed, and radiation resistance. Main memory cells for the MRAM are magnetic memory elements disposed between a write bit line and a write word line. These memory elements are in a stacked structure of multi-layered magnetic metal materials including a soft magnetic layer, a tunnel barrier layer, a hard magnetic layer, and a nonmagnetic conductor layer, which are also referred to as magnetic tunnel junction (MTJ) elements.
Toggle MTJ elements have the advantages of broad operation scope and high thermal stability, which thus are suitable for being applied in embedded systems.
In an MTJ element, it determines to memorize the state “1” or “0” according to the fact that the magnetic moment of two ferromagnetic layers for sandwiching the tunnel barrier layer are in parallel or anti-parallel arrangement. The write data is selected by the intersection of the write bit line (WBL) and write word line (WWL), and a magnetization direction of the magnetic material for a memory layer is changed by the magnetic field generated by the current flowing in the WBL and WWL, such that the resistance is changed, and thereby the data are written.
Referring to FIG. 1A, a typical embodiment of the toggle MTJ element includes an anti-ferromagnetic layer 10, a pinned layer 20 formed on the anti-ferromagnetic layer 10, a tunnel barrier layer 30 formed on the pinned layer 20, and a free layer 40 formed on the tunnel barrier layer 30. The pinned layer 20 and the free layer 40 are both in synthetic anti-ferromagnetic configurations. An upper electrode 51 is formed on the free layer 40, and a lower electrode 52 is formed below the anti-ferromagnetic layer 10. The upper electrode 51 and the lower electrode 52 are connected to a metal wire, so as to form a path for reading data. The WBL and WWL are respectively above the upper electrode 51 and below the lower electrode 52, as shown in FIG. 1B, such that a magnetic field is generated when a write current flows there through. The upper electrode 51 is also connected to a read bit line RBL.
The anti-ferromagnetic layer 10 is made of an anti-ferromagnetic material, e.g., PtMn or IrMn. The pinned layer 20 formed above the anti-ferromagnetic layer 10 is a stack of more than one ferromagnetic layer. The pinned layer 20 shown in FIG. 1A is a three-layered synthetic anti-ferromagnetic fixed layer, which is formed by sequentially stacked ferromagnetic material, non-magnetic metal, and ferromagnetic material, among which the directions of magnetic moments for the two ferromagnetic layers are in the anti-parallel arrangement, for example, CoFe/Ru/CoFe, NiFe/RuNiFe, or CoFeB/Ru/CoFeB respectively. The material of the tunnel barrier layer 30 formed above the pinned layer 20 is, for example, AlOx or MgO. The free layer 40 formed above the tunnel barrier layer 30 may be a stack of more than one layer of ferromagnetic material, which may be NiFe, CoFe, or CoFeB.
In FIG. 1A, the pinned layer 20 includes three layers, i.e., magnetic layers 21 and 23 formed by a ferromagnetic material and an intermediate layer 22 formed by a non-magnetic metal. In addition, the free layer 40 also includes three layers, i.e., magnetic layers 41 and 43 formed by a ferromagnetic material and an intermediate layer 42 formed by a non-magnetic metal. The magnetic layers 41 and 43 in the free layer 40 has magnetic moments 61 and 62 respectively, which are in anti-parallel arrangement through the coupling of the intermediate layer 42. The magnetic layers 21 and 23 in the fixed layer 20 are also in anti-parallel arrangement. The directions of the magnetic moments for the magnetic fields 41 and 43 in the free layer 40 can rotate freely when a magnetic field is applied. However, the magnetization directions of the magnetic layers 21 and 23 in the pinned layer 20 do not rotate when a magnetic field is applied, so the fixed layer 20 functions as a reference layer.
When the data is written, a common method employs two current lines: the write bit line and the write word line, and the memory cells selected by the intersection of induced magnetic fields of the write bit line and the write word line has its resistance changed by changing the magnetization direction of the free layer 40. When the memorized data is read, a current is supplied and flows into the selected magnetic memory cells, so as to read the resistance of the memory cells to determine the digital value of the data.
Due to the anti-parallel coupling effect between the magnetic layers 41 and 43 of the free layer 40, the write operation areas and the writing mode for the toggle MTJ element are as shown in FIGS. 2A and 2B, which is referred to as a first-in-first-out mode. That is, the current conducted first is cut-off first. For example, in FIG. 2, a current IW of the WWL is conducted first before a current IB of the WBL is conducted, so the current IW of the WWL is cut-off first before the current IB of the WBL is cut-off. In FIG. 2B, the situation is just the opposite. The write operation areas 71 and 73 of the toggle MTJ element are as shown in the figures. When the current IW of the WWL is conducted first, the magnetic moments 61 and 62 of the magnetic layers 41 and 43 rotate in a clockwise direction 72; when the current IB of the WBL is conducted first, the magnetic moments 61 and 62 of the magnetic layers 41 and 43 rotate in an counterclockwise direction 74.
In order to improve the speed for the writing operation, U.S. Pat. No. 6,909,631 provides a wiggle waveform. However, such timing process consumes more power to read out data when the data is not written than that consumes by the conventional read-out circuits.
Another method to improve the operation speed utilizes a middle-current reference bit, for example, in U.S. Pat. No. 6,426,907, in which the design is formed by connecting two serially-connected high-resistance MTJ elements and two serially-connected low-resistance MTJ elements in parallel. Thus, the current flowing through a reference bit becomes the middle current. Moreover, A 16 Mb MRAM Featuring Bootstrapped Write Drivers published by J. DeBrosse in IEEE Symp. VLSI Tech., p. 454, 2004 proposes a design formed by connecting a high-resistance MTJ element and a low-resistance MTJ element in parallel, and the current sources connected in parallel are used to evenly divide the current flowing through the reference bit, so as to generate the middle current. A new reference signal generation method for MRAM using a 90 degree rotated MTJ published by W. C. Jeong in IEEE Trans. Magn. Vol. 40. p. 2628, 2004 also proposes a design that takes an MTJ element with magnetic moments of a free layer and a pinned layer being in an orthogonal arrangement as a reference bit, so as to solve the problem that the current flowing through the reference bit deviates from the middle current due to a MR % bias dependent ratio.
The reading circuits in the prior art adopt the design of a common reference bit, so it is not required to turn over the magnetic moment of the free layer for the MTJ element, which thus have advantages of high speed and power saving. However, due to the writing mode of the toggle magnetic memory, the turning-over mode of the magnetic moment of the free layer is a unidirectional cycle. Each time before the writing operation, the stored data must be read to be compared with the data to be written, and then, it is determined whether the subsequent data is to be written or not, so the Read-Before-Write (RBW) process limits the speed for the writing operation.